Standard FlipChip – Bump on I/O

Our Standard Flip Chip (Standard FlipChip) process, formerly known as the Flex-on-Cap (or FoC) process, was originally developed in the mid-1960’s by Delco for use in the automotive industry. Today, the process has unsurpassed industry track record with 40 years and millions of bumped wafers behind it. This is the process to use when you need to place small bumps (less than 130μm in height) directly on the die I/O. Pitch capabilities in this process are typically 150μm or greater for a full array I/O or peripheral I/O design.
Typically, the number of bumps per die ranges from 4 to 6000. The Standard FlipChip process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal constraints of an electroplating process, a wide range of multi-metal solder alloys tailored to your application (such as Sn/Ag/Cu alloys) are available. As with all flip chip die processed with small bumps, these die will require the use of underfilling during packaging in order to achieve acceptable reliability.
To take advantage of this process flow, the device must meet some minimum I/O pad requirements (described in section 3.1.2 of the Design Guide). If the device does not meet these minimum I/O pad requirements, refer to section 3.2, which outlines Standard FlipChip Repassivation alternatives. If you are looking for bump heights greater than 130μm, refer to sections 3.5 and 3.6, and consider the UltraCSP and/or Spheron WLCSP flows. The Standard FlipChip-Bump on I/O process supports fine pitch flip chip applications to pitches well below 100μm.