Cu Pillar Bump – Repassivation (PBO)

As the industry has continued to drive flip chip applications to bump pitches of 150μm and below, significant assembly challenges related to underfilling flip chip assemblies on laminate substrates has arisen due to associated decreases in chip stand-offs. Cu Pillar Flip Chip bumping has emerged as an attractive option both for high end computing and more recently for wireless flip chip, System in Package (SiP) applications, where the predictable stand-off of a copper post can effectively minimize assembly and underfilling problems.
Since FCI is a dominant force in bumping for the wireless electronics space, FCI has developed and qualified a robust Cu Pillar Bump Repassivation technology for use on silicon and GaAs flip chip applications. FCI’s Standard Pillar Bump technology targets applications of 100 micron pitch and greater, while the more recent NANOPillarBump alternative supports ultra-fine pitch flip chip applications down to 35 micron pitch. NANOPillar Bumps target flip chip on silicon applications which are becoming increasingly common in an assortment of 3D packaging schemes.
In order to ensure successful deployment of this product offering, FCI opted to take a Cu Pillar Bump license from APS, a well recognized Singaporean technology company. Unlike the rest of the industry however, FCI’s Cu Pillar Bump offering involves solder capping of plated Cu posts of FlipChip International, LLC Bumping Design Guide Page 15 definable heights, using a minor variant of its widely accepted, proprietary Standard FlipChip printed bump process. This flow uses premixed solder paste for formation of the solder cap and as a result is not limited to the bi-metal constraints of an all electroplating Cu Pillar Bump technology.
Multi-metal alloys (including a broad assortment of Sn/Ag/Cu alloys) can be selected to match the particular requirements of specific applications. The generous die stand-offs that result from Cu Pillar Bumps enable ease of assembly, particularly at underfill. In the case of Flip Chip SiP applications, the elimination of underfill process steps and dimensional design keep outs enabling vacuum-assisted transfer molding for simultaneous die underfilling and package overmolding is enabled.
In this flip chip bumping alternative, a dielectric repassivation layer of either Benzocyclobutene (or BCB) or Spheron can be selected as a localized stress reliever in the bump location on the die before bumping. As with Standard FlipChip-Bump on I/O and Standard FlipChip-Repassivation, FCI’s Cu Pillar Bump – Repassivation offering is designed for small flip chip bumping applications (less than 130μm in diameter) placed directly on the die I/O. FCI’s Cu Pillar Bump can also be readily incorporated with FCI’s plated Cu RDL options should it be required.